发明名称 Processor and method of determining a normalization count
摘要 In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.
申请公布号 US8631056(B2) 申请公布日期 2014.01.14
申请号 US20080971230 申请日期 2008.01.09
申请人 KRITHIVASAN SHANKAR;PLONDKE ERICH JAMES;CODRESCU LUCIAN;ZENG MAO;QUALCOMM INCORPORATED 发明人 KRITHIVASAN SHANKAR;PLONDKE ERICH JAMES;CODRESCU LUCIAN;ZENG MAO
分类号 G06F7/00 主分类号 G06F7/00
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