| 摘要 |
A non-overlap signal generation circuit for a semiconductor memory device which generates two non-overlapped output signals of complementary logic levels with respect to one input signal. The circuit comprises first and second data paths. The first data path includes a first transistor for transiting a first output node from logic "0" to logic "1" when the input signal is transited from logic "0" to logic "1", whereas from logic "1" to logic "0" when the input signal is transited from logic "1" to logic "0", a first inverter for inverting the input signal, and a second transistor for transiting the first output node from logic "1" to logic "0" in response to an output signal from the first inverter. The second data path includes a third transistor for transiting a second output node from logic "0" to logic "1" when the output signal from the first inverter is transited from logic "0" to logic "1", whereas from logic "1" to logic "0" when the output signal from the first inverter is transited from logic "1" to logic "0", a second inverter for inverting the output signal from the first inverter, and a fourth transistor for transiting the second output node from logic "1" to logic "0" in response to an output signal from the second inverter.
|
