发明名称 |
HIERARCHICAL POWER MAP FOR LOW POWER DESIGN |
摘要 |
Power information associated with an IC design is displayed graphically and hierarchically using a power map, thereby providing an intuitive way for describing the power distribution among various power domains of the IC and parent-child relationships within the power domains. Each power domain is associated with a power control for controlling the power domain. The status of the power control for each power domain is displayed on the power map. The power map may include a token to set and display current operating mode of the IC design to enable the IC design to be debugged under different operating modes. |
申请公布号 |
US2014013293(A1) |
申请公布日期 |
2014.01.09 |
申请号 |
US201213718979 |
申请日期 |
2012.12.18 |
申请人 |
SYNOPSYS TAIWAN CO., LTD. |
发明人 |
HSU CHIH-NENG;LIN I-LIANG;FENG WEN-CHI |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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