| 摘要 |
Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information. |
