| 摘要 |
PROBLEM TO BE SOLVED: To prevent extension of execution time of logic simulation due to increase of reporting frequencies while maintaining verification accuracy in logic verification.SOLUTION: In a logic verification system for executing logic simulation to a logic circuit for verification to acquire a generation situation of a predetermined event of interest as coverage, it includes: a logic circuit 211A which performs a logic operation using test data as input to output an arithmetic result; an arithmetic result holding part which holds and outputs the arithmetic result to be output from the logic circuit 211A; an event of interest detection part 214A which detects whether or not an event of interest is generated in the logic circuit 211A based on the arithmetic result to be output from the arithmetic result holding part; and a counter part 215A which counts generation frequencies of the event of interest whenever generation of the event of interest is detected. The counter part 215A outputs a regulated frequency generation report showing that the event of interest for regulated frequencies is generated as coverage when the counted generation frequencies of the event of interest matches to preset regulated frequencies. |
