发明名称 EFFICIENT PARALLEL FLOATING POINT EXCEPTION PROCESSING BY PROCESSOR
摘要 PROBLEM TO BE SOLVED: To efficiently process a floating point exception by a processor which executes an SIMD instruction.SOLUTION: Processing includes the steps of: specifying a numeral exception of an SIMD floating point operation; starting a first SIMD micro operation so as to generate a first Packed part result of the SIMD floating point operation; starting a second SIMD micro operation so as to generate a second Packed part result of the SIMD floating point operation; starting an SIMD unnormalization micro operation so as to put the first and second Packed part results together and to generate a third Packed result having an unnormalized element by unnormalizing a first element of the first and second Packed part results having been put together; storing the third Packed result of the SIMD floating point operation; and setting a flag for specifying the unnormalized element of the third Packed result to the first Packed part result.
申请公布号 JP2014002767(A) 申请公布日期 2014.01.09
申请号 JP20130161489 申请日期 2013.08.02
申请人 INTEL CORP 发明人
分类号 G06F7/76;G06F7/483;G06F9/38 主分类号 G06F7/76
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