| 摘要 |
<p>A level shifter circuit for converting a logic signal with logic '1' and '0' levels at first high and low supply voltage levels to a signal with second high and low supply voltage levels. In particular, the second high and low supply voltage levels are greater than the first high and low supply voltage levels. The disclosed level shifter is configured such that the size of the preceding logic gate and circuitry within the level shifter can be reduced, facilitating its layout in pitch-limited areas. The level shifter also includes circuitry to decouple the output pull-up and pull-down paths to further facilitate state transitions and reduce crowbar current consumption.</p> |
