发明名称 SEMICONDUCTOR MEMORY APPARATUS
摘要 The present invention includes a first chip which includes a refresh generating unit which generates a refresh signal by receiving an external command, a first delay unit which receives and delays the refresh signal through a first penetration electrode, a first selection unit which outputs the output signal of the first delay unit to the first chip through a second penetration electrode in response to a first selection signal, and a second chip which performs a refresh operation by receiving the output signal of the first delay unit and includes a first core area. [Reference numerals] (110) Refresh signal generating unit; (210) First delay unit; (220) First selection unit; (230) First core area; (310) Second delay unit; (320) Second selection unit; (330) Second core area; (410) Third delay unit; (420) Third selection unit; (430) Third core area
申请公布号 KR20140002182(A) 申请公布日期 2014.01.08
申请号 KR20120070005 申请日期 2012.06.28
申请人 SK HYNIX INC. 发明人 KO, JAE BUM
分类号 G11C7/22;G11C5/02;H01L23/48 主分类号 G11C7/22
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