发明名称 Logic die and other components embedded in build-up layers
摘要 Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate comprising a plurality of build-up layers, such as BBUL. In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.
申请公布号 GB201320552(D0) 申请公布日期 2014.01.08
申请号 GB20130020552 申请日期 2013.11.21
申请人 TECHNOLOGY LIMITED;INTEL CORPORATION 发明人
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