发明名称 Feedback scan isolation and scan bypass architecture
摘要 A feedback scan isolation and bypass architecture apparatus and method. The apparatus includes core logic, and input and output multiplexers. The input multiplexer selectively provides a functional input or the core output to the core input based on a test signal. The output multiplexer selectively provides the core output or the input multiplexer output to a functional output based on the test signal. When the test signal indicates core feedback testing, the output multiplexer outputs the core output and the input multiplexer feeds back the core output to the core input. When the test signal indicates bypass testing, the input multiplexer outputs the functional input and the output multiplexer outputs the functional input bypassing the core logic. Logic can block the feedback or bypass signals when there are timing issues. Logic can modify the number of feedback or bypass signals when the number of functional inputs and outputs are different.
申请公布号 US8627159(B2) 申请公布日期 2014.01.07
申请号 US20100944090 申请日期 2010.11.11
申请人 POLICKE PAUL F.;HONG KIM S.;BASSETT PAUL DOUGLAS;QUALCOMM INCORPORATED 发明人 POLICKE PAUL F.;HONG KIM S.;BASSETT PAUL DOUGLAS
分类号 G01R31/28 主分类号 G01R31/28
代理机构 代理人
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