| 摘要 |
Provided is a semiconductor memory apparatus for selectively enabling a plurality of word lines by combining a plurality of sub word line drive signals and a plurality of main word line signals. The semiconductor memory apparatus comprises: a pre-decoding signal generating unit for generating, by decoding an address, a plurality of first pre-decoding signals for generating the plurality of sub word line drive signals and a plurality of second pre-decoding signals for generating the plurality of main word line signals; a signal transmitting unit for outputting, in response to a test signal, the plurality of first pre-decoding signals as a plurality of transmission signals or enabling the plurality of transmission signals irrespective of the plurality of first pre-decoding signals; a sub word line drive decoding unit for generating the plurality of sub word line drive signals in response to the plurality of transmission signals; and a main word line decoding unit for generating the plurality of main word line signals in response to the plurality of second pre-decoding signals. [Reference numerals] (11) First pre-decoding unit; (12) Second pre-decoding unit; (13) Third pre-decoding unit; (14) Fourth pre-decoding unit; (15) Fifth pre-decoding unit; (200) Signal transmitting unit; (310) Sub word line drive decoding unit; (320) Main word line decoding unit |
