发明名称 |
Write-through cache optimized for dependence-free parallel regions |
摘要 |
An apparatus and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller. |
申请公布号 |
US8627010(B2) |
申请公布日期 |
2014.01.07 |
申请号 |
US201213604349 |
申请日期 |
2012.09.05 |
申请人 |
EICHENBERGER ALEXANDRE E.;GARA ALAN G.;OHMACHT MARTIN;SRINIVASAN VIJAYALAKSHMI;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
EICHENBERGER ALEXANDRE E.;GARA ALAN G.;OHMACHT MARTIN;SRINIVASAN VIJAYALAKSHMI |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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