SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF DESIGNING THE SAME, AND METHOD OF FABRICATING THE SAME

摘要

Provided are a method for designing an integrated semiconductor circuit, the integrated semiconductor circuit according to the method, and a manufacturing method thereof capable of minimizing parasitic capacitance generated by an overhead of a gate line. The method for designing the integrated semiconductor circuit comprises a step for performing pre-simulation for the integrated semiconductor circuit; a step for designing a layout including cells and wirings in response to the integrated semiconductor circuit; a step for automatically arranging a cutting area by using an arrangement process; and a step for performing post-simulation based on the layout. The cutting area electrically cuts a conductive line between two device areas. The conductive line is extended through the two device areas in the layout. [Reference numerals] (AA) Start; (BB) End; (S110) Perform pre-simulation; (S130) Design a layout (DRC/LVS); (S150) Arrange a cutting area by using an arrangement process; (S170) Perform post-simulation