发明名称 HIGH-PERFORMANCE INSTRUCTION CACHE SYSTEM AND METHOD
摘要 A method is provided for facilitating operation of a processor core coupled to a first memory containing executable instructions, a second memory faster than the first memory and a third memory faster than the second memory. The method includes examining instructions being filled from the second memory to the third memory, extracting instruction information containing at least branch information; creating a plurality of tracks based on the extracted instruction information; filling at least one or more instructions that possibly be executed by the processor core based on one or more tracks from a plurality of instruction tracks from the first memory to the second memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second memory to the third memory before the processor core executes the instructions, such that the processor core fetches the instructions from the third memory.
申请公布号 WO2014000624(A1) 申请公布日期 2014.01.03
申请号 WO2013CN77889 申请日期 2013.06.25
申请人 SHANGHAI XINHAO MICROELECTRONICS CO. LTD. 发明人 LIN, KENNETH CHENGHAO
分类号 G06F13/16 主分类号 G06F13/16
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