发明名称 HIGH SPEED AND LOW POWER CIRCUIT STRUCTURE FOR BARREL SHIFTER
摘要 <p>A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. The encoding scheme using a sign magnitude to 2's complement converter allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.</p>
申请公布号 WO2014002342(A1) 申请公布日期 2014.01.03
申请号 WO2013JP02394 申请日期 2013.04.08
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM JAPAN, LTD. 发明人 YASUDA, TAKEO
分类号 G06F7/76 主分类号 G06F7/76
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