| 摘要 |
<p>Disclosed is a differential clock signal generator (100) which processes a first differential clock signal (101) using a combination of differential and non-differential components to generate a second differential clock signal (111). Specifically, the first differential clock signal (101) is converted into a single-ended clock signal (103), which is used either by a finite state machine (105) to generate two single-ended control signals (106,107) or by a waveform generator (705) to generate a single-ended waveform control signal (706). In any case, a deskewer (110), which comprises a pair of single-ended latches (201,202) and either multiplexer(s) (250) or logic gates, processes the first differential clock signal (101), the single-ended clock signal (103), and the control signal(s) (106, 107) in order to output a second differential clock signal(l 11) that is different from the first differential clock signal (101) in terms of delay and, optionally, frequency, but synchronously linked to it.</p> |
