According to one embodiment of the present invention, a dual-port SRAM cell comprises: a first cell node; a second cell node; a first inverter of which the output terminal is connected to the first cell node and of which the input terminal in connected to the second cell node; a second inverter of which the output terminal is connected to the second cell node and of which the input terminal is connected to the first cell node; a first pass transistor which is being gate by a first word line and which is connected to the first cell node and a first bit line; a second pass transistor which is being gate by the first word line and which is connected to the second cell node and a first compensation bit line; a third pass transistor which is being gate by a second word line and which is connected to the first cell node and a second bit line; a forth pass transistor which is being gate by the second word line and which is connected to the second cell node and a second compensation bit line; and a first and a second capacitor connected to the first and second nodes respectively. Also, the first and second capacitors can be formed by using a pile layer.
