| 摘要 |
A high-performance data cache system and method is provided for facilitating operation of a processor core. The method includes examining instructions to generate stride length of base register value corresponding to every data access instruction; based on the stride length of base register value, calculating possible a data access address of the data access instruction to be executed next time; based on the calculated the possible data access address of the data access in-struction to be executed next time, prefetching data and filling the data to cache memory before the processor core accesses the data. The processor core may access directly the needed data from the cache memory almost every time, thus getting very high cache hit rate. |
