发明名称 |
DETERMINING CONTROL BITS OF BUTTERFLY NETWORKS FOR PARALLEL TURBO DECODING |
摘要 |
<p>Control bits for switches of a butterfly network are directly solved (314) iteratively for each successive functional column of switches to route data values in parallel according to a multiple access scheme through the butterfly network to memory spaces. A memory space address and appended bus index leading into the butterfly network are generated. A linear order bus index and a physical address are determined for a switch having an unsolved control bit. The solved control bits are applied to solve control bits to a next functional column in a linear order and an interleaved order by starting from the bus index and physical address. The linear order is moved to the interleaved order by a reduced turbo de-interleaver and the interleaved order is moved to the linear order by a reduced turbo interleaver until solving a sequence of control bits related to the start bus index and the start physical address.</p> |
申请公布号 |
WO2014002043(A1) |
申请公布日期 |
2014.01.03 |
申请号 |
WO2013IB55279 |
申请日期 |
2013.06.27 |
申请人 |
RENESAS MOBILE CORPORATION;NIEMINEN, ESKO JUHANI |
发明人 |
NIEMINEN, ESKO JUHANI |
分类号 |
H03M13/27;H03M13/29 |
主分类号 |
H03M13/27 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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