发明名称 |
DATA TRANSFER BETWEEN CLOCK DOMAINS |
摘要 |
An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means (2) clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means (2) detects the predetermined transition in the first clock (ck slow) within the predetermined period of time. |
申请公布号 |
WO2014001765(A1) |
申请公布日期 |
2014.01.03 |
申请号 |
WO2013GB51608 |
申请日期 |
2013.06.20 |
申请人 |
NORDIC SEMICONDUCTOR ASA;SAMUELS, ADRIAN |
发明人 |
HJERTOE, MARKUS BAKKA;BERNTSEN, FRANK |
分类号 |
G06F5/06;G06F1/12 |
主分类号 |
G06F5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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