发明名称 |
MEMORY WITH WORD LINE ACCESS CONTROL |
摘要 |
A memory having a memory array having a plurality of word lines, a plurality of bit cells coupled to the word lines, and a plurality of control memory cells coupled to the word lines. Each word line of the plurality of word lines has a control memory cell coupled thereto and each control memory cell has an output. The memory also has a plurality of logic circuits coupled to the plurality of word lines. The output of each control memory cell is coupled to a corresponding one of the plurality of logic circuits. The plurality of logic circuits prevents access to the word line selected by a row address if the output of the control memory cell coupled to the selected word line is in a first logic state. |
申请公布号 |
US2014003172(A1) |
申请公布日期 |
2014.01.02 |
申请号 |
US201213537209 |
申请日期 |
2012.06.29 |
申请人 |
RAMARAJU RAVINDRARAJ;HOEKSTRA GEORGE P.;RUSSELL ANDREW C. |
发明人 |
RAMARAJU RAVINDRARAJ;HOEKSTRA GEORGE P.;RUSSELL ANDREW C. |
分类号 |
G11C7/22 |
主分类号 |
G11C7/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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