发明名称 STATE SENSING SYSTEM FOR EFUSE MEMORY
摘要 An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.
申请公布号 US2014003120(A1) 申请公布日期 2014.01.02
申请号 US201213535802 申请日期 2012.06.28
申请人 LIAO CHIHHUNG;NGUYEN PHU;PATEL VIMAL R.;PAULIK GEORGE F.;PAULSON PEDER J.;REED BRIAN J.;STORINO SALVATORE N.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 LIAO CHIHHUNG;NGUYEN PHU;PATEL VIMAL R.;PAULIK GEORGE F.;PAULSON PEDER J.;REED BRIAN J.;STORINO SALVATORE N.
分类号 G11C17/16;G06F17/50 主分类号 G11C17/16
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