发明名称 LAYOUT METHOD AND SYSTEM FOR MULTI-PATTERNING INTEGRATED CIRCUITS
摘要 A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.
申请公布号 US2014007026(A1) 申请公布日期 2014.01.02
申请号 US201213535705 申请日期 2012.06.28
申请人 CHEN HUANG-YU;OU TSONG-HUA;HSIEH KEN-HSIEN;HSU CHIN-HSIUNG;TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 CHEN HUANG-YU;OU TSONG-HUA;HSIEH KEN-HSIEN;HSU CHIN-HSIUNG
分类号 G06F17/50 主分类号 G06F17/50
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