SEMICONDUCTOR MEMORY MODULE, MEMORY SYSTEM, CIRCUIT, SEMICONDUCTOR DEVICE AND DIMM

摘要

PROBLEM TO BE SOLVED: To solve a problem that it is hard to synchronize timing since a DQ signal is directly wired from a terminal of DIMM(Dual Inline Memory Module) while a C/A signal in the DIMM is distributed to each DRAM via a register in the DIMM.

SOLUTION: The register is provided to speed up the C/A signal of the DIMM to perform high speed operation and wiring from the register is wired as daisy chain wiring. Then, the sum of delay time from the register to each DRAM and delay amount of a timing adjusting circuit becomes equal to delay time in a DRAM at the farthest end by the timing adjustment circuit provided with wiring delay time difference of the C/A signal and a clock signal different by DRAM locations in the DRAM.

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