High-Speed Sensing Scheme for Memory

摘要

A sensing circuit for use in a memory including memory cells and at least one bitline coupled with the memory cells includes first and second sense amplifiers and a controller coupled with the sense amplifiers. The first sense amplifier is adapted to read a selected one of the memory cells coupled to the first sense amplifier via a corresponding bitline. The second sense amplifier is adapted to read a selected one of the memory cells coupled to the second sense amplifier via a corresponding bitline. The controller selectively connects one of the first and second sense amplifiers in an active path of the memory in a manner which enables one of the sense amplifiers to be operative in a precharge mode and another of the sense amplifiers to be concurrently operative in a sensing mode during a given memory cycle.