发明名称 METHOD AND SYSTEM FOR IMPROVED ANALOG PERFORMANCE IN SUB-100 NANOMETER CMOS TRANSISTORS
摘要 Methods and systems for improved analog performance of core CMOS transistors may comprise a semiconductor die comprising both input/output (I/O) complementary metal oxide semiconductor (CMOS) transistors and core CMOS transistors. A doping profile of a subset of the core CMOS transistors may comprise lightly-doped drain and pocket implant layers between source and drain layers below a gate insulator, and a doping profile of another subset of the core CMOS transistors may be constant between source and drain layer. The core CMOS devices may comprise sub-100 nanometer gate lengths. An output resistance of the second subset of the core CMOS transistors may be increased by the constant doping profile between the source and drain layers. The second subset of the core CMOS transistors may be operable to amplify analog signals. The first subset of the core CMOS transistors may be operable to process digital signals.
申请公布号 US2014001553(A1) 申请公布日期 2014.01.02
申请号 US201313926603 申请日期 2013.06.25
申请人 IMURA KIMIHIKO 发明人 IMURA KIMIHIKO
分类号 H01L27/092;H01L21/8238 主分类号 H01L27/092
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