| 摘要 |
A multiprocessor system includes first through third processors and memory storing address data, all interconnected. In the first processor an access control unit receives the address and the data, and a cache memory storing a cache line including the address, the data and a validity flag. The cache memory invalidates the flag when receiving a request for invalidating the cache line. The access control unit stores the address as a monitoring target when the flag of the cache line is invalidated. When storing a first address included in an invalidated first cache line as a monitoring target, receiving a second address and second data outputted by the third processor is output in response to a request of the second processor, the access control unit judges whether the first address coincides with the second address and relates the first address to the second address to store them when true. |
