| 摘要 |
<p>An embodiment of the invention provides a chip package, which includes a substrate (100) having an upper surface and a lower surface, a chip (102) disposed in or on the substrate, a pad (104) disposed in or on the substrate and electrically connected to the chip, a hole extending from the lower surface toward the upper surface, exposing the pad, wherein a lower opening of the hole near the lower surface has a width that is shorter than that of an upper opening of the hole near the upper surface, an insulating layer (114a) located overlying a sidewall of the hole, and a conducting layer (116) located overlying the insulating layer and electrically connected to the pad.</p> |
