发明名称 |
Method and apparatus for capturing the internal state of a processor for second and higher order speepaths |
摘要 |
A method and apparatus for capturing the internal state of an integrated circuit (IC) for second and higher order speedpath-induced failures. The method includes stretching one or more cycles of an internal clock signal in order to mask a first order speedpath-induced failure (SIF), wherein the internal clock signal is restored to operating at a normal speed subsequent to masking the first order SIF. The internal clock signal may be stopped at a cycle corresponding to a higher order SIF. After stopping the internal clock signal, test output data may be loaded into a scan chain. The method may also be used in conjunction with a laser or other device for other test enhancements.
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申请公布号 |
US7290188(B1) |
申请公布日期 |
2007.10.30 |
申请号 |
US20040930157 |
申请日期 |
2004.08.31 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
PETERSON SPENCER A.;WILCOX RICHARD J.;TABORN MICHAEL P. |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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地址 |
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