| 摘要 |
A method for fabricating an interconnection in a semiconductor device with an MIM(metal insulator metal) capacitor is provided to normally form a via hole between electrodes with a step caused by an etch control layer when a via hole etch process is simultaneously performed on the upper and lower electrodes of an interlayer dielectric by additionally forming an etch control layer on the upper electrode of a capacitor wherein the etch control layer has etch selectivity with respect to the interlayer dielectric. A lower metal layer, an insulator thin film(104a) and an upper metal layer are sequentially formed on an interlayer dielectric of a semiconductor substrate. An etch control layer(108a) is additionally formed on the upper metal layer, having etch selectivity with respect to an interlayer dielectric(110) to be formed afterward. The etch control layer, the upper metal layer and the insulator thin film are patterned. The interlayer dielectric is formed on the resultant structure. The interlayer dielectric and the etch control layer are etched to form a via hole(112) exposing the surface of the upper metal layer while the interlayer dielectric is etched to form a via hole exposing the surface of the lower metal layer. A gap-fill metal layer is filled in the via hole to form a via, and an interconnection connected to the via is formed on the interlayer dielectric. The etch control layer can be made of an insulation layer having etch selectivity with respect to the interlayer dielectric having the via hole.
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