| 摘要 |
A data signal is transferred from a first clock domain, perhaps a first bus bus_slow to a second clock domain, perhaps a second bus bus_fast. The domains comprise respective first and second clocks, the first clock having a frequency ck_slow, typically 32 kHz, which is less than that of the second ck_fast, typically 16 MHz If a predetermined transition, preferably positive, occurs in the first clock within a predetermined period of time, the data signal is transferred again from the first domain to the second. The predetermined period may be between 1 and 16 cycles of the second clock. The transition is detected using means, preferably an edge detector 2, clocked by the second clock. Detection of the transition may comprise discrete sampling of the first clock based on the second clock, possibly with means 4 to count the multiple steps of the discrete sampling. The frequency of discrete sampling may equal the frequency of the second clock. The data signal need not be transferred via the detecting means. |
