| 摘要 |
A butterfly processor architecture including a single high speed multiplier unit and two adder/subtracter units structured to efficiently perform radix-2 decimation-in-time (DIT) butterfly operations is disclosed. The computations for windowing operations, FFT operations, and IFFT operations may be realized in terms of butterfly operations. Therefore, the butterfly processor architecture may be used to perform the computations of a plurality of signal processing operations. The butterfly operations may be performed in-place whereby the results of each operation may be stored in the same location in memory where the inputs for each operation were retrieved. Performing the butterfly operations in-place ensures that the memory may be big enough to hold one frame of data. The butterfly processor architecture may also use scaling elements for implementation of a dynamic scaling algorithm which may reduce the precision requirements of intermediate results when performing signal processing operations and may reduce the data word length.
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