发明名称 |
Progressive circuit evaluation for circuit optimization |
摘要 |
Systems and techniques for optimizing a circuit design are described. Some embodiments reduce the number of gates in the library (e.g., by dynamically pruning the library) which are considered for optimization. Some embodiments create a linear delay model, and use the linear delay model instead of a non-linear delay model to substantially reduce the amount of computation required to check whether or not a particular replacement gate improves one or more metrics of the circuit design. Some embodiments determine an order for processing the gates in the library or for processing input pins of a gate to facilitate early rejection of a candidate gate in the library of gates. In some embodiments, the evaluation of the impact of a candidate gate transformation is done progressively and level-by-level only up to the point where the gate transformation degrades one or more metrics. |
申请公布号 |
US8621408(B2) |
申请公布日期 |
2013.12.31 |
申请号 |
US201213438602 |
申请日期 |
2012.04.03 |
申请人 |
IYER MAHESH A.;WALKER ROBERT;KUNDU SUDIPTO;SYNOPSYS, INC. |
发明人 |
IYER MAHESH A.;WALKER ROBERT;KUNDU SUDIPTO |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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地址 |
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