| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To improve the performance of a signal processor having a multi-core system. <P>SOLUTION: The signal processor is provided with: a plurality of first cache memories; a second memory 103 storing programs 103H-103I for executing respective stages and reservation information for data stored in the first memories and for starting the respective stage programs 103H and 103I; and a plurality of processors performing invalidate processing, signal processing, and writeback processing on the data stored in the first memories and the second memory by starting the respective stage programs 103H-103L. In each processor, reservation information 103B and 103C for starting the second stage program 103I are stored in the second memory in a first stage, and in a second stage, the invalidate processing or the writeback processing is omitted according to pieces of the reservation information 103B and 103C stored in the second memory. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
