发明名称 Device including a clock generation circuit and a method of generating a clock signal
摘要 A device in which a clock generation circuit is connected to a counter circuit for controlling operation timing of a DLL circuit or the like, and the counter circuit is intermittently operated by intermittently supplying a clock signal to the counter circuit from the clock generation circuit.
申请公布号 US8618853(B2) 申请公布日期 2013.12.31
申请号 US201313918172 申请日期 2013.06.14
申请人 ELPIDA MEMORY, INC. 发明人 MIZUKANE YOSHIO;FUJISAWA HIROKI
分类号 H03L7/06 主分类号 H03L7/06
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