| 摘要 |
PROBLEM TO BE SOLVED: To provide a technique for modeling a noise source of a parasitic bipolar transistor and performing a substrate noise analysis without time and cost spent for use of a device simulator.SOLUTION: A circuit simulation is performed to acquire a drain potential and a body potential of an MOS transistor, and based upon the inter-terminal potential difference, a parasitic bipolar transistor which can become a noise source is extracted. From layout information, process information, and the drain potential and body potential, a model of the noise source is created. From the layout information and device information, a substrate model is constructed. They are used for performing a substrate noise analysis. |
