发明名称 |
DECISION FEEDBACK EQUALIZER |
摘要 |
A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit. |
申请公布号 |
US2013346811(A1) |
申请公布日期 |
2013.12.26 |
申请号 |
US201213528877 |
申请日期 |
2012.06.21 |
申请人 |
HUANG MING-CHIEH;CHERN CHAN-HONG;CHUNG TAO WEN;SWEI YUWEN;LIN CHIH-CHANG;HUANG TSUNG-CHING;TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
HUANG MING-CHIEH;CHERN CHAN-HONG;CHUNG TAO WEN;SWEI YUWEN;LIN CHIH-CHANG;HUANG TSUNG-CHING |
分类号 |
G06F1/04;G06F11/00 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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