发明名称 |
FAULT TOLERANT PARALLEL RECEIVER INTERFACE WITH RECEIVER REDUNDANCY |
摘要 |
A communications parallel bus receiver interface having N+1 data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. One of the N+1 data signals comprising a spare data signal when a failure occurs in a corresponding channel transmitting one of N parallel data signals. An input switching network is configured to receive and couple N+1 parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two or three adjacent bit receivers. A calibration device calibrates one of the two or three adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through N+1 receivers for periodic recalibration of each receiver (one at a time) while N+1 inputs are processed continuously and uninterrupted. |
申请公布号 |
US2013343402(A1) |
申请公布日期 |
2013.12.26 |
申请号 |
US201313736353 |
申请日期 |
2013.01.08 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DICKSON TIMOTHY O.;DREPS DANIEL M.;FERRAIOLO FRANK D. |
分类号 |
H04L12/24 |
主分类号 |
H04L12/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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