| 摘要 |
The device has electrodes placed in rows (L0-L8) and in columns (C0-C68) to define pixels of a display cell (1). A control circuit is formed of row, column and clock signal generators to control the rows and the columns. The rows (L0, L8) are short-circuited and regrouped for being controlled by a same control signal from the circuit, in a low power partial display mode. The rows (L1-L7) of an active zone of the cell and the regrouped rows are simultaneously addressed by an active addressing technique at two voltage levels. The levels respectively define a logic level 0 and a logic level 1. |
