发明名称 |
SIMULATING VECTOR EXECUTION |
摘要 |
A system and method for simulating new instructions without compiler support for the new instructions. A simulator detects a given region in code generated by a compiler. The given region may be a candidate for vectorization or may be a region already vectorized. In response to the detection, the simulator suspends execution of a time-based simulation. The simulator then serially executes the region for at least two iterations using a functional-based simulation and using instructions with operands which correspond to P or less lanes of single-instruction-multiple-data (SIMD) execution. The value P is a maximum number of lanes of SIMD exection supported both by the compiler. The simulator stores checkpoint state during the serial execution. In response to determining no inter-iteration memory dependencies exist, the simulator returns to the time-based simulation and resumes execution using N-wide vector instructions. |
申请公布号 |
US2013346058(A1) |
申请公布日期 |
2013.12.26 |
申请号 |
US201213530793 |
申请日期 |
2012.06.22 |
申请人 |
BECKMANN BRADFORD M.;VAISH NILAY;REINHARDT STEVEN K. |
发明人 |
BECKMANN BRADFORD M.;VAISH NILAY;REINHARDT STEVEN K. |
分类号 |
G06F9/45 |
主分类号 |
G06F9/45 |
代理机构 |
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地址 |
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