Selective area growth of germanium and silicon-germanium in silicon waveguides for on-chip optical interconnect applications

摘要

A robust fabrication process for selective area growth of semiconductors in growth windows is provided. Sidewall growth is eliminated by the presence of a spacer layer which covers the sidewalls. Undesirable exposure of the top corners of the growth windows is prevented by undercutting the growth window prior to deposition of the dielectric spacer layer. The effectiveness of this process has been demonstrated by selective-area growth of Ge and Ge/SiGe quantum wells on a silicon substrate. Integration of active optoelectronic devices with waveguide layers via end-coupling through the dielectric spacer layer can be reliably accomplished in this manner.

主权项

1. A method for monolithic integration of dissimilar semiconductor materials, the method comprising:
providing a substrate comprising a first semiconductor layer and one or more primary protective layers disposed on the first semiconductor layer; etching through the primary protective layers into the first semiconductor layer to provide a trench having side walls and a bottom; laterally undercutting at least one of the protective layers by selectively etching the side walls with a side wall etch that preferentially etches the first semiconductor layer with respect to the protective layers; forming a secondary protective layer on the side walls and bottom of the trench; removing the secondary protective layer from the bottom of the trench with a bottom layer etch that completely removes the secondary protective layer on the bottom of the trench and does not completely remove the secondary protective layer on the side walls of the trench; and growing a second semiconductor in the trench, wherein the first semiconductor layer and the second semiconductor have distinct compositions; wherein the substrate comprises a silicon on insulator wafer having a buried oxide layer sandwiched between a silicon substrate and a top silicon layer; wherein the bottom of the trench is in the top silicon layer.