发明名称 |
SCAN TESTING OF INTEGRATED CIRCUITS AND ON-CHIP MODULES |
摘要 |
A method for scan testing an integrated circuit that includes a plurality of on-chip logic modules includes configuring the integrated circuit for module level scan testing and chip level scan testing by way of an external automatic test pattern generator (ATPG) tool. The ATPG tool generates first and second sets of test patterns for module level and chip level scan testing of the integrated circuit. The ATPG tool generates the second set of test patterns by excluding the design faults which have already been targeted during the module level scan testing, from the first set of test patterns and reduces the overall time required for scan testing the integrated circuit. |
申请公布号 |
US2013346819(A1) |
申请公布日期 |
2013.12.26 |
申请号 |
US201213530081 |
申请日期 |
2012.06.21 |
申请人 |
AGGARWAL RAJAN;ANAND ASHUTOSH;BHARGAVA ANKIT;SINGLA MISHIKA;SONONE PRASHANT K.;FREESCALE SEMICONDUCTOR, INC |
发明人 |
AGGARWAL RAJAN;ANAND ASHUTOSH;BHARGAVA ANKIT;SINGLA MISHIKA;SONONE PRASHANT K. |
分类号 |
G01R31/3177 |
主分类号 |
G01R31/3177 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|