Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit

摘要

Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.

主权项

1. A processor comprising:
a plurality of processing cores; an interconnect coupled to the plurality of processing cores; a first logic to assign unique advanced programmable interrupt controller (APIC) identifiers (IDs) to ones of the plurality of processing cores, wherein the assignment is to be formatted into a packet and transmitted on the interconnect; a second logic to detect a state of each of the plurality of processing cores as active or inactive; and a third logic to detect an attribute of each of the plurality of processing cores as eligible to be assigned as the APIC ID or as ineligible to be assigned as the APIC ID, wherein the first logic assigns the APIC ID to the ones of the plurality of processing cores that are active and eligible.