Synchronizing a translation lookaside buffer with an extended paging table

摘要

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

主权项

1. A system comprising:
a flash memory to store instructions and data for performing program execution; a random access memory; and a multi-core processor coupled to the flash memory and the random access memory, the multi-core processor comprising:
a first register to reference a set of page tables, the set of page tables to provide a mapping of guest virtual addresses to guest physical addresses;a second register to reference an active set of extended page tables, including one of:
a first set of extended page tables to provide a mapping of guest physical addresses to host physical addresses for a first virtual machine, the first set of extended page tables to reference a portion of host physical address space associated with the first virtual machine, anda second set of extended page tables to provide a mapping of guest physical addresses to host physical addresses for a second virtual machine, the second set of extended page tables to reference a portion of host physical address space associated with the second virtual machine;address translation logic to access the set of page tables and the set of extended page tables to translate a guest virtual address to a guest physical address and to translate the guest physical address to a host physical address in response to a memory access request including the guest virtual address;a translation look-aside buffer (TLB) to cache a plurality TLB entries, including guest physical address to host physical address translations;execution logic, in response to a TLB invalidate instruction, to invalidate only TLB entries associated with the first virtual machine, independent of corresponding guest physical addresses; andgraphics processing logic.