Reducing data backup and recovery periods in processors

摘要

A low-power processor that does not easily malfunction is provided. Alternatively, a low-power processor having high processing speed is provided. Alternatively, a method for driving the processor is provided. In power gating, the processor performs part of data backup in parallel with arithmetic processing and performs part of data recovery in parallel with arithmetic processing. Such a driving method prevents a sharp increase in power consumption in a data backup period and a data recovery period and generation of instantaneous voltage drops and inhibits increases of the data backup period and the data recovery period.

主权项

1. A processor comprising:
an instruction decoder; a logic unit including a plurality of logic circuit blocks including a volatile memory block and a nonvolatile memory block; a backup/recovery controller including a storage storing first reference instruction enumeration and second reference instruction enumeration; a power controller; and a flag storage, wherein the instruction decoder receives an instruction from an outside of the processor and gives an instruction to the logic unit, the backup/recovery controller, and the power controller, wherein, when enumeration of the instruction from the outside of the processor corresponds to at least part of the first reference instruction enumeration, the backup/recovery controller gives an instruction to back up data from the volatile memory block to the nonvolatile memory block to at least one of the plurality of logic circuit blocks in accordance with the first reference instruction enumeration, wherein the backup/recovery controller receives an instruction from the instruction decoder and gives an instruction to recover data from the nonvolatile memory block to the volatile memory block to at least one of the plurality of logic circuit blocks in accordance with the second reference instruction enumeration, wherein one of the logic circuit blocks in the logic unit receives an instruction from the backup/recovery controller, and performs data backup or data recovery between the volatile memory block and the nonvolatile memory block, wherein another one of the logic circuit blocks in the logic unit concurrently receives an instruction from the instruction decoder and performs arithmetic processing using data stored in the volatile memory block, wherein a data backed up flag or a data recovered flag is written to the flag storage by the backup/recovery controller, and wherein the power controller receives an instruction from the instruction decoder or the backup/recovery controller and powers on or off the logic unit.