Non-mounted storage test device based on FPGA

摘要

A non-mounted storage test device based on FPGA includes a processor unit for performing enumeration and configuration for device, creating a scenario for test and performing test; a device driver unit for managing storage device; a data engine unit for generating pattern data for test and performing test; a system memory interface unit for receiving data for test and storing test result; a monitoring unit for monitoring packet; a DMA driver/address translation unit for performing DMA operation and transmitting Memory Read Request to Root Complex; a message input/output unit for transmitting to the data engine unit and the device driver unit; a switch unit for constituting DUT unit; a storage-in DUT unit as device under test which is storage for direct interface to PCIe including HBA; and a memory unit for storing data for test and record generated between tasks.

主权项

1. A non-mounted storage test device based on FPGA (Field-Programmable Gate Array), comprising:
a processor unit configured, as a microprocessor embedded inside FPGA, for performing enumeration and configuration for device of PCIe (Peripheral Component Interconnect Express) bus tree below RC (Root Complex), setting the device driver unit by creating a scenario for test, and performing test; a device driver unit, as block generating ATA (Advanced Technology Attachment) command used in storage device based on the test scenario created by the processor unit, for communicating with HBA (Host Bridge Adapter) including AHCI (Advanced Host Controller Interface) managing storage device; a data engine unit for generating pattern data to be used for test, and performing test by accessing to data stored by user from system memory; a system memory interface unit for receiving data needed to proceed test by accessing to the memory by the processor unit and the data engine unit and storing test result; a monitoring unit for monitoring packet of PCIe transaction layer and storing this in case of occurrence of test failure; a DMA (Direct Memory Access) driver/address translation unit for performing DMA operation that all data stream become HBA Master, and transmitting Memory Read Request to Root Complex including the device driver unit when the device driver unit decodes the scenario and transmits commands to HBA through PCIe bus; a message input/output unit for transmitting to the data engine unit and the device driver unit in case TLP (Transaction Layer Packet) coming up to Bus PCIe RC (Root Complex) is message as reading result of the DMA driver/address translation unit; a PCIe SW IP (Software Intellectual Property) unit as SW IP of PCI Express logic; a switch unit for constituting DUT (Device Under Test) unit by connecting to the PCIe IP unit; a storage-in DUT unit as device under test which is storage for direct interface to PCIe including HBA; and a memory unit for storing data to be used in test and record generated between tasks.