| 主权项 |
1. A resistive random-access memory device, comprising:
a memory array, comprising a plurality of memory cells, wherein each memory cell comprises at least one non-volatile memory unit; a read circuit, coupled to one of a select bit-line and a select word-line, wherein the select bit-line and the select word-line are electrically connected to a selected memory cell among the memory cells, and the read circuit reads data stored in the selected memory cell and generates a first control signal according to a resistance state of the selected memory cell; a write-back circuit, performing a write-back operation on the selected memory cell according to a write-back control signal and a write-back voltage, so as to change the resistance state of the selected memory cell from a low resistance state to a high resistance state, and generating a second control signal according to the resistance state of the selected memory cell; and a write-back logic circuit, coupled to the read circuit and the write-back circuit and generating the write-back control signal according to the first control signal and the second control signal, wherein the write-back control signal is set to a value to cause the write-back circuit to perform the write-back operation when both the first control signal and the second control signal indicate the low resistance state of the selected memory cell, wherein the write-back logic circuit comprises:
a first flip-flop, receiving and latching the first control signal and outputting the first control signal at a falling or rising edge of a read control signal; anda first logic circuit, coupled to the first flip-flop and comprising at least a logic gate to perform a logic operation on the first control signal output by the first flip-flop and the second control signal to generate the write-back control signal, and wherein the high and low resistance states respectively correspond to a high and low logic level of the selected memory cell. |
