Controlling the voltage level on the word line to maintain performance and reduce access disturbs

摘要

A semiconductor memory storage data device and method of use (e.g SRAM) comprising: a plurality of storage cells 65 having port access control device(s) 60 responsive to an access control line (wordline WL); access control (word control) circuitry comprising switching circuitry (30,fig 2) configured to connect a selected access control line to one or more voltage sources (VDDB, VDDS) and feedback circuitry (inverter 50) configured to feedback a change in voltage on the access control line (WL) to the access switching circuitry 52,40,45. The access control circuitry is configured to respond to a data access request Xp to access a selected storage cell 65. This involves controlling the access switching circuitry to provide a low impedance connection (e.g MOSFET devices 40, 45 on) between the voltage source (VDDB, VDDS) and the access control line (WL) such that a voltage level on the access control line (WL) changes towards the predetermined access voltage level at a first rate; and in response to the feedback circuitry (50) providing a feedback signal indicating that the access control line voltage has attained a predetermined (threshold) value to control the access control switching circuitry to provide a higher impedance connection (only MOSFET device 45 on) between the voltage source and the access control line, such that a voltage level on the access control line WL changes towards the predetermined access voltage level for devices 60 at a second rate, the second rate being slower than the first rate. Hence a dual slope or double gradient is observed on the word line during memory cell activation. FinFET transistors may be used in the memory storage devices.