| 摘要 |
Provided is one embodiment of a semiconductor structure. The semiconductor structure a semiconductor substrate; an shallow trench isolation (STI) feature, wherein the STI feature is a continuous feature and includes a first portion in a first region and a second portion in a second region, and the first portion of the STI feature is recessed relative to the second portion; an active region bordered by the STI feature on the semiconductor substrate; a gate stack disposed on the active region and extending to the first region of the STI feature in a first direction; source and drain features formed in the active region and interposed by the gate stack; and a channel formed in the active region and spanned between the source and drain features in a second direction, wherein the second direction is different from the first direction. The channel includes a top portion having the width W in the first direction and two side portions each having the height H less than the width W. [Reference numerals] (132) Provide a semiconductor substrate;(134) Form a shallow trench isolation (STI) feature for defining a plurality of semiconductor regions on the semiconductor substrate;(136) Form at least one dummy gate in the semiconductor region;(138) Form source and drain features;(140) Form an inter-layer dielectric (ILD) on the semiconductor substrate;(142) Remove the dummy gate to form a gate trench on the ILD;(144) Recess a STI feature in the gate trench by selective etching;(146) Form a gate stack on the gate trench |
