发明名称 Vertical junction field effect transistors having sloped sidewalls and methods of making
摘要 592399 Disclosed is a semiconductor device. The device includes a substrate of a semiconductor material of a first conductivity type and a channel layer above an upper surface of the substrate. The channel layer has two or more raised regions, each extending upward from adjacent channel layer surfaces such that the raised regions each have an upper surface and first and second sidewalls. The first and second sidewalls of each of the raised regions in the vicinity of the adjacent channel layer surfaces taper inward from vertical to form an angle of at least 5° from vertical to the upper surface of the substrate. In the vicinity of the upper surface of the respective raised region, the first and second sidewalls taper inward at an angle of <50 from vertical to the upper surface of the substrate. Each of the raised regions includes an inner portion of a semiconductor material of a first conductivity type, and outer portions of a material of a second conductivity type different from the first conductivity type. The outer portions are beneath the first and second sidewalls. Gate regions of material of the second conductivity type lie beneath the adjacent channel layer surfaces and contiguous with the outer portions of the raised regions. A source layer of a material of the first conductivity type lies above each of the upper surfaces of the raised regions.
申请公布号 NZ592399(A) 申请公布日期 2013.12.20
申请号 NZ20090592399 申请日期 2009.11.05
申请人 POWER INTEGRATIONS INC. 发明人 SHERIDAN DAVID C.;RITENOUR ANDREW P.
分类号 H01L29/78;H01L21/336;H01L29/10;H01L29/808 主分类号 H01L29/78
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